1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device having an output buffer for executing data output.
2. Description of the Background Art
Semiconductor integrated circuit devices applied to various electronics execute operations in accordance with instructions and output the resulting data signals. In such a case, the data signal output from a semiconductor integrated circuit devices are driven by an output buffer, with consideration given to an output load from a subsequent circuit receiving the data signal.
FIG. 16 is a schematic block diagram showing a configuration of a conventional semiconductor integrated circuit device 1 including output buffers.
Referring to FIG. 16, semiconductor integrated circuit device 1 includes an internal circuit 2 and output buffers 3, 4. The semiconductor integrated circuit device outputs data signals D1 and D2 from output nodes 5 and 6, respectively, based on output data Dr from internal circuit 2 output in response to an operation instruction.
Data signals D1 and D2 are supplied to different destinations, so that output loads LD1 and LD2 at the respective output nodes 5 and 6 are also different from each other. Output loads LD1 and LD2 correspond to the line capacitance between the respective nodes and the subsequent circuits to be supplied with data signals D1 and D2, the input capacitance in the respective subsequent circuits, and so forth.
Internal circuit 2 generates data level control signals Dh and Dl indicating the level of output data Dr output in response to the operation instruction. Data level control signal Dh is activated to be at a logic low level (hereinafter simply referred to as L level) when output data Dr is at a logic high level (hereinafter simply referred to as H level). On the other hand, data level control signal Dl is activated to be at the H level when output data Dr is at the L level.
Output buffers 3 and 4 drive data signals D1 and D2 onto output nodes 5 and 6, respectively, in accordance with data level control signals Dh and Dl output from internal circuit 2.
Output buffer 3 includes a P-channel transistor 7a and an N-channel transistor 7b. P-channel transistor 7a is turned on in response to the activation (to the L level) of data level control signal Dh, to form a current path between output node 5 and a power-supply voltage Vcc. N-channel transistor 7b is turned on in response to the activation (to the H level) of data level control signal Dl, to form a current path between output node 5 and a ground voltage Vss.
Output buffer 4 has a configuration similar to that of output buffer 3, and includes an N-channel transistor 8a and a P-channel transistor 8b. P-channel transistor 8a is turned on in response to the activation (to the L level) of data level control signal Dh, to form a current path between output node 6 and power-supply voltage Vcc. N-channel transistor 8b is turned on in response to the activation (to the H level) of data level control signal Dl, to form a current path between output node 6 and ground voltage Vss.
In each of output buffers 3 and 4, the amount of current on the current path formed between a voltage according to the level of output data Dr and the associated output node 5 or 6, i.e. a current drivability of an output buffer, corresponds to the sizes of the transistors constituting each output buffer.
FIGS. 17A and 17B each schematically shows a relationship between the current drivability of an output buffer and a change in the voltage of a data signal.
In FIGS. 17A and 17B, an example of a voltage change of output node 5 is shown, in which output buffer 3 outputs data signal D1 of the H level.
FIG. 17A illustrates a waveform in the case where the current drivability of the output buffer is small with respect to the output load. Referring to FIG. 17A, at time ta, data level control signal Dh is activated to be at the L level in order to set data signal D1 to be at the H level. In response to the activation, P-channel transistor 7a within output buffer 3 forms a current path between power-supply voltage Vcc and output node 5 with a current drivability corresponding to the size of the transistor.
However, when the size of P-channel transistor 7a is small and thus the current drivability of the output buffer is small with respect to output load LD1, the voltage of output node 5 is increased in a gentle slope, requiring relatively long time period xcex94t1 before the voltage of output node 5 exceeds a predetermined voltage Vr corresponding to the H level data at time tb.
Thus, if the current drivability of the output buffer is excessively small, the voltage of output node 5 cannot change rapidly, reducing the speed of the data output, and hence the specification such as access time may not be satisfied.
Whereas, in FIG. 17B, a waveform in the case where the current drivability of the output buffer is excessively large with respect to the output load. Referring to FIG. 17B, at time ta, data level control signal Dh is activated to be at the L level. In response to the activation, P-channel transistor 7b within output buffer 3 forms a current path between ground voltage Vss and output node 5 with a current drivability corresponding to the size of the transistor.
However, when the size of P-channel transistor 7b is large and thus the current drivability of the output buffer is excessively large with respect to output load LD1, the voltage of output node 5 is rapidly increased. Therefore, time period xcex94t2 needed before the voltage of output node 5 exceeds predetermined voltage Vr at time tc is shortened, allowing a high-speed data output. However, such a rapid change in the voltage involving an overshoot or undershoot may generate noise, which would adversely affect the operation of a subsequent circuit.
Therefore, it is necessary to design the current drivability of each output buffer to be at an appropriate value in accordance with a corresponding output load, so as not to cause the action as shown in FIGS. 17A and 17B.
Referring again to FIG. 16, in the conventional semiconductor integrated circuit device 1, in order to change the current drivability of each of output buffers 3 and 4, the sizes of transistors 7a, 7b, 8a and 8b constituting the output buffers must be changed, which involves a design change or mask revision at manufacturing of the device. Thus, enormous cost and time are needed for adjustment of the current drivability of the output buffer.
In order to solve such problems and to make the current drivability of the output buffer easily adjustable, Japanese Patent Laying-Open No. 7-38408 (hereinafter also referred to as Document 1) discloses, in FIGS. 2 and 3, the configuration of an output buffer using a plurality of transistors connected in parallel.
The output buffer shown in FIG. 2 of Document 1 includes a plurality of transistors arranged in parallel with each other for supplying current to an output terminal, and a plurality of fuse units respectively connected between the gates of these transistors and an input terminal. Such an arrangement allows adjustment of the amount of driving current of the output buffer, by adjusting the number of activated transistors by cutting-off of the fuse units.
However, the arrangement of the output buffer shown in FIG. 2 of Document 1 has a problem of positioning of the fuse units. If the fuse units are arranged in a region adjacent to transistor elements constituting the output buffer, constraint in the layout design will be severe. Moreover, increase of the level of a blow input for ensuring cut-off of the fuse units may adversely affect the circuit portion of the output buffer.
If, on the other hand, the fuse units are concentrated in a specific region to ensure both secure cutting-off of the fuse units and elimination of the adverse effect on the other circuit portions, the time required for operation in the output buffer will be increased. This is because signals are propagated to the gates of the transistors constituting the output buffer through the fuse units.
The output buffer shown in FIG. 3 of Document 1 further includes a plurality of transistors arranged in parallel with each other for supplying current to an output terminal, and fuse units connected in series with the respective transistors. However, such an arrangement also causes a similar problem concerning the positioning of the fuse elements. In addition, the cut-off state of the fuse units may be a factor of variation in the amount of current supplied to the output terminal, possibly inhibiting stable operation.
Japanese Patent Laying-Open No. 8-125519 (hereinafter also referred to as Document 2) discloses, in FIG. 2, the configuration of a semiconductor device in which the current drivability of an output buffer is adjusted by a control circuit including a fuse.
In the semiconductor device shown in FIG. 2 of Document 2, a plurality of output current adjusting units are arranged in parallel with an output buffer circuit. Each output current adjusting unit is set to be in an activated state by cutting off the fuse included in a corresponding control circuit.
However, in the semiconductor device disclosed in Document 2, the output data from an IC circuit unit is transmitted to the gate of the transistor constituting the output buffer circuit via one stage of inverter, whereas it is transmitted to the gate of the transistor constituting each output current adjusting unit via an NAND gate. This results in different time periods for data propagation from the IC circuit unit to the gate of the transistor constituting the output current adjusting unit and to the gate of the transistor constituting the output buffer circuit.
Thus, in such a semiconductor device, the current path is formed between the output buffer circuit and the output terminal at a timing different from the timing at which the current path is formed between the current adjusting unit and the output terminal. This makes it difficult to adjust the data output timing at the output terminal, possibly causing unstabilized operation.
Furthermore, recently, a semiconductor integrated circuit device has been developed in which a plurality of chips are embedded in the same package to bring out a new function by combining the chips.
For example, there are a semiconductor integrated circuit device in which two chips of Dynamic Random Access Memories (DRAM) are contained within one package to double the capacity of the device; a semiconductor integrated circuit device in which two or four chips are mounted on one package to enlarge the bus width; and a semiconductor integrated circuit device in which a Static Random Access Memory (SRAM) and a flash memory are mounted in lamination on one package to enable the flash memory to be driven by an access to the SRAM. In particular, the one in which a plurality of chips are laminated is also referred to as a Multi-Chip Package (MCP).
In such an MCP semiconductor integrated circuit device, noise due to an output data signal has an increased effect on the circuit mounted on the other chips. Therefore, it is necessary to sufficiently adjust circuit operation conditions represented by a current drivability of an output buffer, and to efficiently set the adjusted operation conditions at the time of actual operation.
It is an object of the present invention to provide a configuration of a semiconductor integrated circuit device including an output buffer capable of easily adjusting a current drivability while securing operation stability.
Another object of the present invention is to efficiently set operation conditions of a circuit in a semiconductor integrated circuit device of a multi-chip package configuration including a plurality of chips.
According to an aspect of the present invention, a semiconductor integrated circuit device outputting data having first and second levels includes an internal circuit and an output buffer. The internal circuit outputs data to an internal node. The output buffer outputs the data read from the internal circuit onto the internal node to an output node. The output buffer includes a plurality of first current driving units, a plurality of second current driving units, a plurality of operation selection units, a plurality of first signal transmission units, and a plurality of second signal transmission units. The plurality of first current driving units are connected in parallel with each other between the voltage corresponding to the first level and the output node. Each of the first current driving units forms a current path between the voltage corresponding to the first level and the output node, in accordance with a voltage of a corresponding control node. The plurality of second current driving units are connected in parallel with each other between a voltage corresponding to the second level and the output node. Each of the second current driving units forms a current path between the voltage corresponding to the second level and the output node, in accordance with a voltage of a corresponding control node. The plurality of operation selection units are provided respectively corresponding to the plurality of first and second current driving units, and each of the plurality of operation selection units sets a corresponding one of the plurality of first and second current driving units in a non-volatile manner to be in one of activated and inactivated states at least after completion of an wafer manufacturing process. The plurality of first signal transmission units are provided respectively corresponding to the plurality of first current driving units, and each of the plurality of first signal transmission units transmits the level of the read data from the internal node to a control node of a corresponding first current driving unit with a first propagation time period, when a corresponding first current driving unit is in the activated state. The plurality of second signal transmission units are provided respectively corresponding to the plurality of second current driving units, and each of the plurality of second signal transmission units transmits the level of the read data from the internal node to a control node of a corresponding second current driving unit with a second propagation time period, when the corresponding second current driving unit is in the activated state.
Therefore, a main advantage of the present invention is that the first and second current driving units included in the output buffer can be selectively set to be in the activated or inactivated state in latter steps of the manufacturing process. Thus, the current drivability of the output buffer can easily be adjusted reflecting the noise effects on the other circuits, variation at manufacturing and so forth, without any change of design or mask revision. Moreover, the generalized design can be accommodated to a wide range of output loads, enabling alleviation of design load, reduction of inventory or the like. In addition, in each of the first and second current driving units that is set to be in the activated state, the signal propagation time period from the internal node to the control node is similarly set. Therefore, at least one of the first or second current driving units driving current onto the output node can be set to have a similar operation timing, to attain stabilized operation.
According to another aspect of the present invention, a semiconductor integrated circuit device having a plurality of chips enclosed within the same package includes an internal circuit, a memory circuit and a coupling unit. The internal circuit is formed on one of the plurality of chips. The memory circuit is formed on another one of the plurality of chips and is capable of, at least, reading of stored data. The coupling unit electrically couples the internal circuit and the memory circuit. The internal circuit operates in accordance with an operation condition set based on the stored data read from the memory circuit.
Therefore, the operation condition of the internal circuit mounted on one of the embedded plurality of chips can efficiently be set without execution of a non-volatile program inputting operation, e.g. without undergoing a fuse-blowing step.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.